The present invention relates to a reference cell for reading EEPROM memory devices.
As is known, for reading memory cells of EEPROM devices reference cells (also known as "dummy cells") are frequently used for generating the read voltage of said memory cells. Said read voltage must be comprised between the threshold voltage of a written cell (i.e. charged with positive charges in the floating gate) and the threshold voltage of an erased cell (i.e. charged with negative charges in the floating gate). Since the reference cells are manufactured during the same process for making the memory cells and are operated in the same conditions as said memory cells, they are capable of "following" the variations of process parameters (e.g. the increase in the current delivered by a cell due to different oxide thicknesses, all other parameters being equal) and the operating conditions so as to ensure an exact reading of the memory device.
For this purpose, virgin cells, i.e. cells which are never programmed in one way or the other, are currently used as reference cells, since they have a characteristic which is comprised between the characteristic of written cells and that of erased cells (see FIG. 1).
For allowing said virgin cells to reliably and accurately perform their task, they must keep their threshold voltage constant throughout the device entire life. However, various factors can have a negative effect so as to vary their characteristics.
In particular, it is known that during silicon working said silicon is subjected to strong electric fields and to ion bombardment. This entails that at the end of the process the floating gates (and therefore the gate of the reference cell as well) are charged in a random manner, thus varying the electric characteristics of the reference cell.
Furthermore, it is also known that floating gates can be electrostatically charged during the operations for packaging the finished devices.
Further problems can arise during the life of the device, due to oscillations of the voltage applied to the reference cell, which can cause the introduction of charges into the floating gate of the latter.
Various solutions have been proposed in order to solve the above described problems. One of them provides exposure of the processed wafers to ultraviolet rays before the final check test. This exposure requires the use of a passivation which is transparent to ultraviolet rays and is simultaneously impermeable to moisture, with obvious disadvantages as regards greater structural complexity and costs for the execution of this method step.
Another solution entails the use of particular devices and procedures during the packaging step in order to reduce the electrostatic charges. This solution is also not free from disadvantages, due to the greater costs related to the special devices and to the need to provide special procedures.
Finally, it has also been proposed to eliminate the tunnel element, i.e. the thin oxide region (100 .ANG.) between the floating gate and the drain region of the reference cell, so as to prevent accidental programming due to the Fowler-Nordheim effect. In this manner, however, the morphology of the reference cell differs appreciably from that of the cells of the memory array. In particular, sensitivity to variations in the thickness of the tunnel oxide, which is a parameter of primary importance in determining capacitive couplings, is lost.